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CXB1810FN
Post Amplifier for Optical Fiber Communication Receiver
Description The CXB1810FN achieves 2R optical fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is equipped with a signal detection function, and outputs at TTL level. Features * Auto-offset canceler circuit * Signal interruption alarm output * Single 3.3V or 5.0V power supply Applications SONET/SDH Absolute Maximum Ratings * Supply voltage VCC - VEE * Input voltage difference | VD - VDN | * ECL/TTL output current (Continuous) (Surge) * Storage temperature Tj 16 pin HSOF (plastic)
-0.3 to +6.0 2.5 50 70 -65 to +150
V V mA mA C
Recommended Operating Conditions * Supply voltage VCC - VEE 3.14 to 5.25 * Termination voltage (for Q/QB) Vt1 VCC - 1.8 to Vcc - 2.2 * Termination resistance (for Q/QB) Rt 46 to 56 * Operating temperature Ta -40 to +85
V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99801D26-PS
CXB1810FN
Block Diagram
VEEO VccO Q QB
1 2 3 4 16 Vcc 15 D 14 DB 13 VEE 12 CAP1
SDC
5
11 CAP1B
SDCB
6 10 SW
CAP3
7 9 DOWN
CAP2
8
Pin Configuration
DOWN 9 SW 10 CAP1B 11 CAP1 12 VEE 13 DB 14 D 15 VCC 16
8 7 6 5 4 3 2 1
CAP2 CAP3 SDCB SDC QB Q VCCO VEEO
-2-
CXB1810FN
Pin Description Pin No. 1 2 Typical pin voltage (V) Symbol DC AC VEEO VccO 0 3.3 or 5.0
VCCO
Equivalent circuit
Description Ground for data output circuit. Positive power supply for data output circuit.
3 4
Q QB
1.7 to 2.4 or 3.4 to 4.1
3
Data outputs.
4
VEEO
VCC
5
SDC
0.2 to 2.9 or 0.2 to 4.7
5
Signal detection output (TTL). The SDC output is driven to low level while signal interruption is detected.
VEE
VCC
6
SDCB
0.2 to 2.9 or 0.2 to 4.7
6
Signal detection output (TTL). The SDCB output is driven to high level while signal interruption is detected.
VEE
7
CAP3
1.3 to 1.8 or 3.0 to 3.5 1.6 or 3.3
VCC
7
8
Connect a peak hold capacitor for the signal detection circuit. 470pF (typ.)
8
CAP2
VEE
-3-
CXB1810FN
Pin No.
Typical pin Symbol voltage (V) DC AC
Equivalent circuit
Description
VCC
9
2.4 or DOWN 4.1
9
Connect a resistor between this pin and the VCC pin to decrease the signal detection level from the default value.
VEE
VCC
10
SW
10
VEE
Switches the maximum identification voltage amplitude. This pin is set to 50mVp-p (single ended) when open or high level, or to 15mVp-p (single ended) when low level. Setting to low level is recommended when using a resistor of 510 or less between the VCC and DOWN pins.
VCC
11 12
CAP1B 2.2 or 3.9 CAP1
15 14 12 11
Connect an external capacitor between these pins. 0.022F (typ.)
14 15
DB D
VEE
Data inputs.
13 16
VEE VCC
0 3.3 or 5.0
Ground. Positive power supply.
-4-
CXB1810FN
Electrical Characteristics DC Characteristics Item Q/QB high output voltage Q/QB low output voltage Q/QB output amplitude Symbol VOH1 VOL1 Vp (VCC = 3.14 to 5.25V, Ta = -40 to +85C, unless otherwise specified) Conditions 51 terminated to VCC - 2V 51 terminated to VCC - 2V 51 terminated to VCC - 2V IOH = -0.2mA IOL = 2.1mA Min. VCC - 1100 VCC - 1800 500 2.4 0.5 VCC - 0.3 VEE During single-phase input 1000 33 All outputs open 50 40 69 55 VCC VEE + 0.3 Typ. Max. Unit
VCC - 650 mV VCC - 1300 mV 1000 mVp-p V V V V mVp-p mA
SDC/SDCB high output voltage VOHT SDC/SDCB low output voltage VOLT SW high input voltage SW low input voltage Maximum input voltage amplitude D/DB input resistance Supply current VIHT VILT Vmax Rin ICC
AC Characteristics Item Limiting amplifier gain Signal detection threshold voltage Signal detection hysteresis width
(VCC = 3.14 to 5.25V, Ta = -40 to +85C, unless otherwise specified) Symbol GL Vth P Tas Tdas TR TF 51 terminated to VCC - 2V 51 terminated to VCC - 2V During single ended input 3 0 2.3 130 110 Conditions Min. 45 34 6 8 100 100 Typ. Max. Unit dB mVp-p dB s s ps ps
Signal detection response assert time1 Signal detection response deassert time1 Q/QB rise time (20 to 80%) Q/QB fall time (20 to 80%)
1 Data = PN23 - 1 pattern, 100mVp-p single ended, Rd = open, CAP2/CAP3 = 470pF
-5-
CXB1810FN
DC Electrical Characteristics Measurement Circuit
2V 1 2 16 15 14 13
V
51 51 3 4
V
V
12
V
5
11
V
6 10 470pF 7 9 470pF 8
V
3.14 to 5.25V
-6-
CXB1810FN
AC Electrical Characteristics Measurement Circuit
50 input Oscilloscope
1 ZO = 50 ZO = 50 2 3 4 16 0.01F 15 14 0.01F 13 12 5 11 0.022F
6 10
7 470pF 9 8 470pF
Hi-Z input Oscilloscope
2V
-1.14 to -3.25V
-7-
CXB1810FN
Application Circuit
1 2 3 4 16
51
0.01F 15 14 0.01F 13 12 5 11 0.022F
6 10 470pF 7 9 470pF 8
3.3/5.0V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
-8-
CXB1810FN
Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with an auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and internal resistor R1 determine the input low cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and internal resistor R2 determine the high cut-off frequency for DC feedback. Since a peak may occur in the low frequency area of the gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of this peak. The typical values of R1, R2, C1 and C2 are indicated below. Also, when a single ended input is used, provide AC grounding by connecting Pin 14 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 50 f2: 318kHz C1 (external): 0.01F C2 (external): 0.022F R2 (internal): 10k f1: 723Hz
C1 15 To inside the IC C1 14 R1 12 C2 11 R2 R1 R2
Fig. 1
DC feedback frequency response
Amplifier frequency response
Gain
f1
f2
Frequency
Fig. 2 -9-
CXB1810FN
2. Alarm block In this block, the input signal amplitude is detected and the signal interruption alarm is output when the amplitude becomes lower than the set alarm level. The alarm level setting can be adjusted by connecting an external resistor Rd between the DOWN and VCC pins. Also, this IC can set the maximum identification voltage amplitude to two levels. The maximum identification voltage amplitude is set to 50mVp-p (single ended) when the SW pin is open or high level, or to 15mVp-p (single ended) when the SW pin is low level. Figs. 15 and 16 show the relation of Rd and the alarm assert/deassert level. Setting the SW pin to low level is recommended when Rd is 510 or less.
VDAS Deassert level VAS Assert level High level SD output SW High SW Low
Low level
VDAS 3dB 3dB
VAS 15 50
Hysteresis
Input voltage (mVp-p, single phase)
Fig. 3
Fig. 4
In addition, the SD response deassert time is guaranteed only under the conditions noted in the AC Electrical Characteristics item, but the response becomes delayed as the input signal amplitude becomes larger. This is because the input resistor R1 shown in Fig. 1 is small at 50, so the charge accumulated in C2 is relatively large and the discharge time for this charge accounts for most of the SD response deassert time. The SD response deassert time can be shortened by using the external circuit shown in Fig. 5 or by shorting the CAP1 and CAP1B pins. However, care should be taken as the auto-offset canceler circuit does not operate in this case causing the reception sensitivity to deteriorate. Fig. 14 shows the relation between the SD response deassert time and the electrical input amplitude when using the connection shown in Fig. 5.
C1 15 100 C1 14 R1 1.5k 12 C2 1.5k 11 R2 R2 R1 To inside the IC
Fig. 5 - 10 -
CXB1810FN
3. Substrate layout The exposed metal portions on the rear surface of the package used for the CXB1810FN are electrically connected to the silicon substrate. Superior thermal radiation characteristics can be obtained by connecting the rear surface of the package and these exposed metal portions to the ground surface on the PCB. Providing lands directly below the package as shown in the figure below and connecting as many thermal vias as possible to the inner layer ground surface is recommended.
0.4mm
0.25mm
1.45mm
0.75mm
2.0mm
4. Other * Be careful when handling this IC as its electrostatic discharge strength is weak. * Be sure to connect all power supply pins (VCCO, VCC) and ground pins (VEEO, VEE) to power supplies or grounds, respectively. For example, if only VCCO is left open and power is supplied to the other pin, the IC may malfunction.
- 11 -
CXB1810FN
Example of Representative Characteristics
ICC vs. Supply voltage
41.5 Ta = 40C Output pins open 41.0 42.0 41.5 41.0 40.5 ICC [mA] 40.0 39.5 39.0 38.5 38.0 37.5 38.5 3.0 3.5 4.0 4.5 5.0 5.5 37.0 -40 -20 0 20 40 VCC = 3.14V VCC = 5.25V 60 80 100 VCC = 3.14V/5.25V Output pins open
ICC vs. Temperature
40.5 ICC [mA]
40.0
39.5
39.0
VCC [V]
Ta [C]
Fig. 6
Q/QB output voltage vs. Supply voltage
-0.8 Q/QB output voltage [V, ref to VCC] Q/QB output voltage [V, ref to VCC] -0.9 Ta = 40C -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 3.0 3.5 4.0 4.5 5.0 5.5 -0.6
Fig. 7
Q/QB output voltage vs. Temperature
VCC = 3.14V/5.25V -0.8
-1.0 H level (VCC = 3.14V) H level (VCC = 5.25V) L level (VCC = 3.14V) L level (VCC = 5.25V)
-1.2
-1.4
-1.6
-1.8 -40
-20
0
20
40
60
80
100
VCC [V]
Ta [C]
Fig. 8
Q/QB output voltage amplitude vs. Supply voltage
0.700 Q/QB output voltage amplitude [Vp-p] Q/QB output voltage amplitude [Vp-p] 0.695 0.690 0.685 0.680 0.675 0.670 0.665 0.660 0.655 0.650 3.0 3.5 4.0 4.5 5.0 5.5 Vp-p, Ta = 40C 0.700 0.695 0.690 0.685 0.680 0.675 0.670 0.665 0.660 0.655 0.650 -40 -20 0
Fig. 9
Q/QB output voltage amplitude vs. Temperature
VCC = 3.14V/5.25V
VCC = 3.14V VCC = 5.25V 20 40 60 80 100
VCC [V]
Ta [C]
Fig. 10
Fig. 11
- 12 -
CXB1810FN
SDC/SDCB output voltage vs. Supply voltage
6 Ta = 40C, IOH = -0.2mA, IOL = +2.1mA SDC/SDCB output voltage [V]
SDC/SDCB output voltage vs. Temperature
6 VCC = 3.14V/5.25V, IOH = -0.2mA, IOL = +2.1mA 5
SDC/SDCB output voltage [V]
5
4
4
3
3
2
2
1
1
H level (VCC = 3.14V) H level (VCC = 5.25V) L level (VCC = 3.14V) L level (VCC = 5.25V)
0
3.0
3.5
4.0
4.5
5.0
5.5
0 -40
-20
0
20
40
60
80
100
VCC [V]
Ta [C]
Fig. 12
Input voltage amplitude vs. SD response deassert time
350 300 SD response deassert time [s] 250 200 150 100 50 0 Recommended circuit Fig. 5 connection
Fig. 13
0
0.2
0.4
0.6
0.8
1.0
1.2
Input voltage amplitude [mVp-p, single ended]
Fig. 14
- 13 -
CXB1810FN
Rd vs. SD assert/deassert level
SD assert/deassert level [mVp-p, single ended] VCC = 3.3V SW = H level 50 SD assert/deassert level [mVp-p, single ended] 60 16 14 12 10 8 6 4 2 0 100
Rd vs. SD assert/deassert level
VCC = 3.3V SW = L level
40
30
20 VAS VDAS
10 0 0.1 1 Rd [k] 10
VAS VDAS 200 300 400 Rd [] 500 600 700
100
Fig. 15
SD assert/deassert level vs. Supply voltage
SD assert/deassert level [mVp-p, single ended] SD assert/deassert level [mVp-p, single ended] 60 60
Fig. 16
SD assert/deassert level vs. Temperature
50 Ta = 40C, DOWN pin open, SW = H level
50 VCC = 3.14V/5.25V, DOWN pin open, SW = H level
40
40
30
30
20 VAS VDAS 10
20 VAS (VCC = 3.14V) VDAS (VCC = 3.14V) VAS (VCC = 5.25V) VDAS (VCC = 5.25V) -20 0 20 40 60 80 100
10
0
3.0
3.5
4.0
4.5
5.0
5.5
0 -40
VCC [V]
Ta [C]
Fig. 17
SD assert/deassert level vs. Supply voltage
SD assert/deassert level [mVp-p, single ended] SD assert/deassert level [mVp-p, single ended] 30 30
Fig. 18
SD assert/deassert level vs. Temperature
25 Ta = 40C, Rd = 2k, SW = H level
25 VCC = 3.14V/5.25V, Rd = 2k, SW = H level
20
20
15
15
10
10 VAS (VCC = 3.14V) VDAS (VCC = 3.14V) VAS (VCC = 5.25V) VDAS (VCC = 5.25V) -20 0 20 40 60 80 100
5
VAS VDAS 3.0 3.5 4.0 4.5 VCC [V] 5.0 5.5
5
0
0 -40
Ta [C]
Fig. 19
Fig. 20
- 14 -
CXB1810FN
SD assert/deassert level vs. Supply voltage
SD assert/deassert level [mVp-p, single ended] SD assert/deassert level [mVp-p, single ended] 14 12 10 8 6 4 2 0 VAS VDAS Ta = 40C, Rd = 510, SW = L level 14 12 10 8 6 4 2
SD assert/deassert level vs. Temperature
VCC = 3.14V/5.25V, Rd = 510, SW = L level
VAS (VCC = 3.14V) VDAS (VCC = 3.14V) VAS (VCC = 5.25V) VDAS (VCC = 5.25V) -20 0 20 40 60 80 100
3.0
3.5
4.0
4.5
5.0
5.5
0 -40
Ta [C]
Ta [C]
Fig. 21
SD assert/deassert level vs. Supply voltage
SD assert/deassert level [mVp-p, single ended] SD assert/deassert level [mVp-p, single ended] 7 6 5 4 3 2 1 0 VAS VDAS 3.0 3.5 4.0 4.5 VCC [V] 5.0 5.5 Ta = 40C, Rd = 150, SW = L level 7 6 5 4 3 2 1 0 -40
Fig. 22
SD assert/deassert level vs. Temperature
VCC = 3.14V/5.25V, Rd = 150, SW = L level
VAS (VCC = 3.14V) VDAS (VCC = 3.14V) VAS (VCC = 5.25V) VDAS (VCC = 5.25V) -20 0 20 40 60 80 100
Ta [C]
Fig. 23
Input amplitude vs. Bit error rate (VCC = 3.3V)
1.00E-03 1.00E-04 1.00E-05 Bit error rate 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 2.0 Ta = -40C Ta = 0C Ta = 40C Ta = 85C Bit error rate 1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 1.00E-10 2.0
Fig. 24
Input amplitude vs. Bit error rate (VCC = 5.0V)
Ta = -40C Ta = 0C Ta = 40C Ta = 85C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input amplitude [mVp-p, single ended]
Input amplitude [mVp-p, single ended]
Fig. 25
Fig. 26
- 15 -
CXB1810FN
Q output waveform VCC = 3.3V, Ta = 40C D = 100mVp-p (single ended) PN23 pattern
100mV/div
100ps/div
Fig. 27
Q output waveform VCC = 5.0V, Ta = 40C D = 100mVp-p (single ended) PN23 pattern
100mV/div
100ps/div
Fig. 28
Q output waveform VCC = 3.3V, Ta = 40C D = 10mVp-p (single ended) PN23 pattern
100mV/div
100ps/div
Fig. 29
Q output waveform VCC = 5.0V, Ta = 40C D = 10mVp-p (single ended) PN23 pattern
100mV/div
100ps/div
Fig. 30
- 16 -
CXB1810FN
Package Outline
Unit: mm
HSOF 16PIN(PLASTIC)
0.9 0.1 5.6 0.1 A
16 9
0.05 S
(5.5) (3.1)
3.8 0.1 4.4 0.1
1
8
0.65 0.05 M S A
(1.5) (0.7) (0.5)
S
(0.2)
(4.4)
(0.2)
Solder Plating
(0.2)
+ 0.1 0.32 - 0.03 B
+ 0.1 0.26 - 0.03 DETAILB
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.06g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
HSOF-16P-02
Kokubu & SCT Ass'y
HSOF 16PIN(PLASTIC)
0.9 0.1 5.6 0.1 A
16 9
0.2
(0.2)
+ 0.05 0 0.2 + 0.05 0 (1.75) 0.45 0.15
0.05 S
(5.5) (3.1)
3.8 0.1 4.4 0.1
1
8
0.65 0.05 M S A
(1.5) (0.7) (0.5)
S
(0.2)
(4.4)
Solder Plating
B
+ 0.1 0.26 - 0.03 DETAILB
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.06g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
HSOF-16P-02
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m
- 17 -
(0.2)
+ 0.1 0.32 - 0.03
(1.75)
0.45 0.15
Sony Corporation

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